When output is at logic 1 , pull up structure for the output stage is ON state & it provides a path from VDD to output.
NMOS has half the resistance of an equal sized PMOS. If PMOS resistance is 2R. NMOS resistance
is R.
NAND gate has 2 NMOS are connected in series, 2 PMOS are in parallel. So pull up, pull down
resistance will be
Pull up resistance = 2R||2R= R (Parallel)
Pull down resistance = R+R= 2R (Series)
Similarly NOR gate ,
Pull up resistance = 2R+2R =4R
Pull down resistance = R||R = R/2
*NAND gate has better ratio of output high drive and output low drive as
compared to NOR gate. Hence NAND is preferred.
*To use NOR gate as universal gate either pull or pull down structure has to be
resized (decrease the length of PMOS cells or increase length of NMOS cells)
to have similar resistance as resistance is directly proportional to length
(R =ρL/A)
)
NMOS has half the resistance of an equal sized PMOS. If PMOS resistance is 2R. NMOS resistance
is R.
NAND gate has 2 NMOS are connected in series, 2 PMOS are in parallel. So pull up, pull down
resistance will be
Pull up resistance = 2R||2R= R (Parallel)Pull down resistance = R+R= 2R (Series)
Similarly NOR gate ,
Pull up resistance = 2R+2R =4R
Pull down resistance = R||R = R/2
*NAND gate has better ratio of output high drive and output low drive as
compared to NOR gate. Hence NAND is preferred.
*To use NOR gate as universal gate either pull or pull down structure has to be
resized (decrease the length of PMOS cells or increase length of NMOS cells)
to have similar resistance as resistance is directly proportional to length
(R =ρL/A)
)
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