Guide, Region and Fence

Guide, Region and Fence :

 Guide:

• Guide is assigned with certain cells (standard cells or macros) in the design.

• Allows the cells assigned to it to move outside if required.

• It allows the other cells to sit inside it.

• Soft constraint.

                                          

Region:

• Region is assigned with certain cells (standard cells or macros) in the design.

• It does not all the cells assigned to it to be placed outside.

• It allows the other cells to sit inside it.

• Soft constraint.

Fence:

• Fence is assigned to certain cells in the design.

• It does not allow other cells inside.

• It does not allow the cells assigned to it outside.

• Hard constraint.

Guide, Region, and Fence are used in Cadence Innovus. Whereas Bounds are used in Synopsys.

Difference between short channel MOSFET and long channel MOSFET?

Short Channel MOSFET:

1. This come under Deep submicron transistor.
2.The gate length is less than 250nm
3.Width and length of the channel is short.
4.Vt is dependent of channel length L
   and width W

Long channel MOSFET:

1. This come under submicron transistor.
2.The gate length is greater than 250nm
3.Width and length of the channel is short.
4.Vt is independent of channel length L
   and width W

Why NAND structures are preferred over NOR ones ?

When output is at logic 1 , pull up structure for the output stage is ON state & it provides a path from VDD to output.

NMOS has half the resistance of an equal sized PMOS. If PMOS resistance is 2R. NMOS resistance
is R.

NAND gate has 2 NMOS are connected in series, 2 PMOS are in parallel. So pull up, pull down
resistance will be

Pull up resistance = 2R||2R= R (Parallel)
Pull down resistance = R+R= 2R (Series)


Similarly NOR gate ,

Pull up resistance = 2R+2R =4R
Pull down resistance = R||R = R/2

*NAND gate has better ratio of output high drive and output low drive as
  compared to NOR gate. Hence NAND is preferred.

*To use NOR gate as universal gate either pull or pull down structure has to be
   resized (decrease the length of PMOS cells or increase length of NMOS cells)
   to have similar resistance as resistance is directly proportional to length
   (R =ρL/A)

)

Why PMOS aspect ratio is greater than NMOS in CMOS?

Reasons:

1. We know, Electrons has mobility 2.7 times higher the holes.

2. Since hole mobility is lesser than electron mobility, PMOS width must be greater to compensate

    and make the pull-up network stronger.

3.If W to L of PMOS is same as the corresponding NMOS, the charging time of the output node

   would be higher than that of the discharging time (related to NMOS)

     

       W/L to PMOS is 2 or 3 times the W to L of NMOS.

STANDARD CELL

WHAT IS STANDARD CELL-BASED, APPLICATION SPECIFIC
INTEGRATED CIRCUIT (ASIC) DESIGN
METHODOLOGY?

Logic synthesis is the process of transforming the chip’s RTL description into a technology-dependent gate netlist by using the library’s logical view. In contrast to RTL description, which only contains functional information, the gate netlist is the standard cell representation of the design at the component level. It is comprised of gate instances and port connectivity among these instances. The primary requirement for the task of logic synthesis is ensuring the mathematical equivalency between the synthesized gate netlist and the original RTL description.

The process of place is the first step in creating the chip in a physical domain. It determines the physical locations of each individual cell in the netlist based on design constraints. Placement is a complicated process that is very algorithm intensive and time-consuming. The quality of the placement work has a preeminent impact on the chip’s performance. The following route process is also critical. It creates the physical wire connections for the signal and power nets that are defined in the logic connectivity of the netlist. It is a very complicated process whose goals include meeting the design speed target, minimizing the total wire length, and avoiding the design rule violations.