STANDARD CELL

WHAT IS STANDARD CELL-BASED, APPLICATION SPECIFIC
INTEGRATED CIRCUIT (ASIC) DESIGN
METHODOLOGY?

Logic synthesis is the process of transforming the chip’s RTL description into a technology-dependent gate netlist by using the library’s logical view. In contrast to RTL description, which only contains functional information, the gate netlist is the standard cell representation of the design at the component level. It is comprised of gate instances and port connectivity among these instances. The primary requirement for the task of logic synthesis is ensuring the mathematical equivalency between the synthesized gate netlist and the original RTL description.

The process of place is the first step in creating the chip in a physical domain. It determines the physical locations of each individual cell in the netlist based on design constraints. Placement is a complicated process that is very algorithm intensive and time-consuming. The quality of the placement work has a preeminent impact on the chip’s performance. The following route process is also critical. It creates the physical wire connections for the signal and power nets that are defined in the logic connectivity of the netlist. It is a very complicated process whose goals include meeting the design speed target, minimizing the total wire length, and avoiding the design rule violations.